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Data Sheet
Table 37. STATUS1 Register (Address 0xE503)
ADE7880
Bit
0
Mnemonic
NLOAD
Default Value
0
Description
When this bit is set to 1, it indicates that at least one phase entered no load
condition determined by the total active power and apparent power. The phase is
indicated in Bits[2:0] (NLPHASE[x]) in the PHNOLOAD register (see Table 41.)
1
FNLOAD
0
When this bit is set to 1, it indicates that at least one phase entered no load
condition based on fundamental active and reactive powers. The phase is indicated
in Bits[5:3] (FNLPHASE[x]) in the PHNOLOAD register (see Table 41).
2
VANLOAD
0
When this bit is set to 1, it indicates that at least one phase entered no load
condition based on apparent power. The phase is indicated in Bits[8:6]
(VANLPHASE[x]) in the PHNOLOAD register (see Table 41).
3
4
5
6
7
8
9
ZXTOVA
ZXTOVB
ZXTOVC
ZXTOIA
ZXTOIB
ZXTOIC
ZXVA
0
0
0
0
0
0
0
When this bit is set to 1, it indicates a zero crossing on Phase A voltage is missing.
When this bit is set to 1, it indicates a zero crossing on Phase B voltage is missing.
When this bit is set to 1, it indicates a zero crossing on Phase C voltage is missing.
When this bit is set to 1, it indicates a zero crossing on Phase A current is missing.
When this bit is set to 1, it indicates a zero crossing on Phase B current is missing.
When this bit is set to 1, it indicates a zero crossing on Phase C current is missing.
When this bit is set to 1, it indicates a zero crossing has been detected on Phase A
voltage.
10
ZXVB
0
When this bit is set to 1, it indicates a zero crossing has been detected on Phase B
voltage.
11
ZXVC
0
When this bit is set to 1, it indicates a zero crossing has been detected on Phase C
voltage.
12
ZXIA
0
When this bit is set to 1, it indicates a zero crossing has been detected on Phase A
current.
13
ZXIB
0
When this bit is set to 1, it indicates a zero crossing has been detected on Phase B
current.
14
ZXIC
0
When this bit is set to 1, it indicates a zero crossing has been detected on Phase C
current.
15
RSTDONE
1
In case of a software reset command, Bit 7 (SWRST) is set to 1 in the CONFIG register,
or a transition from PSM1, PSM2, or PSM3 to PSM0, or a hardware reset, this bit is set
to 1 at the end of the transition process and after all registers changed value to
default. The IRQ1 pin goes low to signal this moment because this interrupt cannot
be disabled.
16
SAG
0
When this bit is set to 1, it indicates one of phase voltages entered or exited a sag
state. The phase is indicated by Bits[14:12] (VSPHASE[x]) in the PHSTATUS register
(see Table 40).
17
OI
0
When this bit is set to 1, it indicates an overcurrent event has occurred on one of the
phases indicated by Bits[5:3] (OIPHASE[x]) in the PHSTATUS register (see Table 40).
18
OV
0
When this bit is set to 1, it indicates an overvoltage event has occurred on one of the
phases indicated by Bits[11:9] (OVPHASE[x]) in the PHSTATUS register (see Table 40).
19
SEQERR
0
When this bit is set to 1, it indicates a negative-to-positive zero crossing on Phase A
voltage was not followed by a negative-to-positive zero crossing on Phase B voltage
but by a negative-to-positive zero crossing on Phase C voltage.
20
MISMTCH
0
When this bit is set to 1, it indicates ISUM ? INWV > ISUMLVL , where
ISUMLVL is indicated in the ISUMLVL register.
21
22
23
Reserved
Reserved
PKI
1
0
0
Reserved. This bit is always set to 1.
Reserved. This bit is always set to 0.
When this bit is set to 1, it indicates that the period used to detect the peak value in
the current channel has ended. The IPEAK register contains the peak value and the
phase where the peak has been detected (see Table 34).
Rev. A| Page 91 of 104
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